Power consumption during operation of a silicon microchip can be reduced using silicon on insulator (SOI) technology. The use of SOI technology can not only result in lower power consumption but also in an increased speed of operation of integrated circuits due to a reduction in stray capacitance. For SOI structures, thin layers of silicon on insulator can be fabricated using several well known techniques such as separation by implantation of oxygen (SIMOX), separation by plasma implantation of oxygen (SPIMOX), silicon on sapphire (SOS), bonded wafer processes on silicon, and silicon bonded on sapphire.
Bonded wafer processes on silicon involve technologies to bond monocrystalline silicon materials onto semiconductor wafers and oxidation processes to form the semiconductor on insulator. In these technologies, a portion of one or both of the bonded wafers is removed, typically, by polishing methods. Another process to remove large portions of a bonded wafer uses a “smart cut” technology. “Smart cut” technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized to crack the substrate.